Field
The disclosed embodiments relate to computer systems. More specifically, the disclosed embodiments relate to techniques for ordering memory commands in computer systems based on the latency of the memory commands and/or other properties of the memory commands.
Related Art
A number of memory technologies are associated with latencies that vary by memory location and/or type of memory access. For example, one region (i.e., physical area) of memory may have consistently higher latencies than another region of memory in the same computer system. As a result, a memory operation involving one region of memory may have a different latency than a memory operation involving another region of memory. Similarly, write commands may have significantly higher latencies than read commands. Thus, a high-latency write command to a memory bank may block a number of critical read commands to the same memory bank. These variations in latency may further be affected by factors such as process variations, temperature, wear-out levels, error-correcting logic, and/or density modes of memory cells. The variation in latencies may interfere with the efficient scheduling and/or execution of memory commands in computer systems.
In the figures, like reference numerals refer to the same figure elements.